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fn6800 rev 10.00 page 1 of 23 december 8, 2016 fn6800 rev 10.00 december 8, 2016 isl28114, isl2 8214, isl28414 single, dual, quad general purpose micropower, rrio operational amplifiers datasheet the isl28114 , isl28214 , and isl28414 are single, dual, and quad channel general purpose micropower, rail-to-rail input and output operational amplifiers with supply voltage range of 1.8v to 5.5v. key features are a low supply current of 390a maximum per channel at room temperature, a low bias current, and a wide input voltage range, which enables the isl28x14 devices to be excellent general purpose op amps for a wide range of applications. the isl28114 is available in the sc70-5 and sot23-5 packages, the isl28214 is in the msop8, so8, and sot23-8 packages, and the isl28414 is in the tssop14 and soic14 packages. all devices operate across the extended temperature range of -40c to +125c. related literature ? for a full list of related documents, visit our website - isl28114 , isl28214 and isl28414 product pages features ? low current consumption . . . . . . . . . . . . . . . . . . . . . . . . 390a ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v ? gain-bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . . . 5mhz ? input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . 20pa, max. ? operating temperature range. . . . . . . . . . . .-40c to +125c ?packages - isl28114 (single). . . . . . . . . . . . . . . . . . . . sc70-5, sot23-5 - isl28214 (dual) . . . . . . . . . . . . . . . . msop8, so8, sot23-8 - isl28414 (quad) . . . . . . . . . . . . . . . . . . . soic14, tssop14 applications ? power supply control/regulation ? process control ? signal gain/buffers ? active filters ? current shunt sensing ?transimpedance amp in- in+ r f r ref + isl28x14 +5v v- v+ r in - 10k r in + 10k - + 100k vref 100k v out load r sense single-supply, low-side current sense amplifier gain = 10 figure 1. typical application
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 2 of 23 december 8, 2016 ordering information part number ( note 4 ) part marking tape and reel (units) package (rohs compliant) pkg. dwg. # isl28114fez-t7 ( notes 1 , 2 )bka ( note 5 ) 3k 5 ld sc-70 p5.049 isl28114fez-t7a ( notes 1 , 2 )bka ( note 5 ) 250 5 ld sc-70 p5.049 isl28114fhz-t7 ( notes 1 , 2 )bdba ( note 5 ) 3k 5 ld sot-23 p5.064a isl28114fhz-t7a ( notes 1 , 2 )bdba ( note 5 ) 250 5 ld sot-23 p5.064a isl28214fuz ( note 2 ) 8214z - 8 ld msop m8.118a isl28214fuz-t7 ( notes 1 , 2 ) 8214z 1.5k 8 ld msop m8.118a isl28214fbz ( note 2 ) 28214 fbz - 8 ld soic m8.15e isl28214fbz-t7 ( notes 1 , 2 ) 28214 fbz 1k 8 ld soic m8.15e isl28214fbz-t13 ( notes 1 , 2 ) 28214 fbz 2.5k 8 ld soic m8.15e isl28214fhz-t7 ( notes 1 , 3 )bela ( note 5 ) 3k 8 ld sot-23 p8.064 isl28214fhz-t7a ( notes 1 , 3 )bela ( note 5 ) 250 8 ld sot-23 p8.064 isl28414fvz ( note 2 ) 28414 fvz - 14 ld tssop mdp0044 isl28414fvz-t7 ( notes 1 , 2 ) 28414 fvz 1k 14 ld tssop mdp0044 isl28414fvz-t13 ( notes 1 , 2 ) 28414 fvz 2.5k 14 ld tssop mdp0044 isl28414fbz ( note 2 ) 28414 fbz - 14 ld soic mdp0027 isl28414fbz-t7 ( notes 1 , 2 ) 28414 fbz 1k 14 ld soic mdp0027 isl28414fbz-t13 ( notes 1 , 2 ) 28414 fbz 2.5k 14 ld soic mdp0027 ISL28114SOT23EVAL1Z evaluation board isl28214msopeval2z evaluation board isl28214soiceval2z evaluation board isl28414tssopeval1z evaluation board notes: 1. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and nipdau plate-e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), see device information page for isl28114 , isl28214 , isl28414 . for more information on msl, see tech brief tb363 . 5. the part marking is located on the bottom of the part.
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 3 of 23 december 8, 2016 pin configurations isl28114fez (5 ld sc-70) top view isl28114 (5 ld sot-23) top view isl28214 (8 ld msop, 8 ld soic, 8 ld sot-23) top view isl28414 (14 ld tssop, 14 ld soic) top view in+ v s - in- v s + out 1 2 3 5 4 out v s - in+ v s + in- 1 2 3 5 4 out_a in-_a in+_a v s - v s + out_b in-_b in+_b 1 2 3 45 6 7 8 out_a in-_a in+_a v s + in+_b in-_b out_b out_d in-_d in+_d v s - in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 pin descriptions pin name pin number description circuits 5 ld sc-70 5 ld sot-23 8 ld msop, 8 ld soic, 8ldsot-23 14 ld tssop, 14 ld soic out out_a out_b out_c out_d 41 1 7 1 7 8 14 output circuit 1 v s - 2 2 4 11 negative supply voltage circuit 2 in+ in+_a in+_b in+_c in+_d 13 3 5 3 5 10 12 positive input circuit 3 in- in-_a in-_b in-_c in-_d 34 2 6 2 6 9 13 negative input v s + 5 5 8 4 positive supply voltage see ? circuit 2 ? v+ v- out v+ v- capacitively triggered esd clamp in+ in- v+ v-
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 4 of 23 december 8, 2016 absolute maximum ratings (t a = +25 c) thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5v supply turn-on voltage slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1v/s differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma differential input voltage . . . . . . . . . . . . . . . . . . . . . . .v - - 0.5v to v + + 0.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v - - 0.5v to v + + 0.5v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kv machine model (isl28114, isl28214) . . . . . . . . . . . . . . . . . . . . . . . 350v machine model (isl28414). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv thermal resistance (typical) ? ja (c/w) ? jc (c/w) 5 ld sc-70 ( notes 6 ) . . . . . . . . . . . . . . . . . . 250 n/a 5 ld sot-23 ( notes 6 ) . . . . . . . . . . . . . . . . . 225 n/a 8 ld msop ( notes 6 , 7 ) . . . . . . . . . . . . . . . . 180 100 8 ld soic package ( notes 6 , 7 ) . . . . . . . . . 126 90 8 ld sot-23 package ( notes 6 , 7 ) . . . . . . . 240 168 14 ld tssop package ( notes 6 , 7 ) . . . . . . 120 40 14 ld soic package ( notes 6 , 7 ) . . . . . . . . 90 50 ambient operating temperature range . . . . . . . . . . . . . .-40c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ? ja is measured with the component mounted on a high-effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications v s + = 5v, v s - = 0v, r l = open, v cm = v s /2, t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c, unless otherwise specified. parameter description test conditions min ( note 8 )typ max ( note 8 )unit dc specifications v os input offset voltage -4 0.5 4 mv -40c to +125c -5 5 mv tcv os input offset voltage temperature coefficient -40c to +125c 5 v/c i os input offset current 130 pa i b input bias current isl28114 -20 3 20 pa -100 100 pa isl28214, isl28414 -20 3 20 pa -50 50 pa common-mode input voltage range - 0.1 5.1 v cmrr common-mode rejection ratio v cm = -0.1v to 5.1v 72 db -40c to +125c 70 db psrr power supply rejection ratio v s = 1.8v to 5.5v 71 db -40c to +125c 70 db v oh output voltage swing, high r l = 10k 4.985 4.993 v 4.98 v v ol output voltage swing, low r l = 10k 13 15 mv 20 mv v + supply voltage 1.8 5.5 v i s supply current per amplifier r l = open 300 390 a 475 a i sc+ output source short-circuit current r l = 10 to v- -31 ma i sc- output sink short-circuit current r l = 10 to v+ 26 ma
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 5 of 23 december 8, 2016 ac specifications gbwp gain-bandwidth product v s = 2.5v a v = 100, r f = 100k , r g =1k , r l = 10k to v cm 5mhz e n v p-p peak-to-peak input noise voltage v s = 2.5v f = 0.1hz to 10hz 12 v p-p e n input noise voltage density v s = 2.5v f = 1khz 40 nv/ (hz) v s = 2.5v f = 10khz 16 nv/ (hz) i n input noise current density v s = 2.5v f = 1khz 8fa/ (hz) z in input impedance 10 12 c in differential input capacitance v s = 2.5v f = 1mhz 1.0 pf common-mode input capacitance 1.3 pf transient response sr slew rate v out = 0.5v to 4.5v 2.5 v/s t r , t f , small signal rise time, t r 10% to 90% v s = 2.5v a v = +1, v out = 0.05v p-p ? r f =0 , r l = 10k ?? c l = 15pf 37 ns fall time, t f 10% to 90% 42 ns t s settling time to 0.1%, 4v p-p step v s = 2.5v a v = +1, r f = 0 ?? r l =10k ?? c l = 1.2pf 5.6 s note: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization, and/or design. electrical specifications v s + = 5v, v s - = 0v, r l = open, v cm = v s /2, t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c, unless otherwise specified. (continued) parameter description test conditions min ( note 8 )typ max ( note 8 )unit
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 6 of 23 december 8, 2016 typical performance curves v s = 2.5v, v cm = 0v, r l = open, unless otherwise specified. figure 2. input bias current vs temperature figure 3. input noise voltage spectral density figure 4. open-loop gain, phase vs frequency, r l =100k ? , c l = 10pf, v s = 0.9v figure 5. open-loop gain, phase vs frequency, r l = 100k ? , ? c l = 10pf, v s = 2.5v figure 6. cmrr vs frequency (simulated data) figure 7. psrr vs frequency, v s = 0.9v, 2.5v -50 -40 -30 -20 -10 0 10 20 30 40 50 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i bias (pa) simulation frequency (hz) 10 100 1000 input noise voltage (nv/ ? hz) 1 10 100 1k 10k 100k 10,000 v+ = 2.5v a v = 1 -80 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open-loop gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 phase () r l = 100k simulation c l = 10pf phase gain v + = 0.9v -80 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open-loop gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 phase () r l = 100k simulation c l = 10pf phase gain v + = 0.9v 0 10 20 30 40 50 60 70 80 0.01 0.1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db) simulation 1 psrr (db) frequency (hz) 100 1k 10k 100k 1m 10m 0 10 20 30 40 50 60 70 80 90 r l = inf a v = +1 v cm = 100mv p-p c l = 4pf psrr- v s = 0.9v psrr- v s = 2.5v psrr+ v s = 2.5v psrr+ v s = 0.9v
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 7 of 23 december 8, 2016 figure 8. frequency response vs closed-loop gain figure 9. frequency response vs v out figure 10. gain vs frequency vs r l figure 11. gain vs frequency vs c l figure 12. gain vs frequency vs supply voltage figure 13. crosstalk, v s = 2.5v typical performance curves v s = 2.5v, v cm = 0v, r l = open, unless otherwise specified. (continued) frequency (hz) gain (db) 100k 1m 10m 10 10k 1k 100 100m v + = 2.5v v out = 50mv p-p c l = 4pf r l = 10k a v = 1 a v = 100 a v = 1000 r g = 100, r f = 100k a v = 10 r g = open, r f = 0 r g = 1k, r f = 100k r g = 10k, r f = 100k -10 0 10 20 30 40 50 60 70 normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m 100m v s = 2.5v a v = +1 r l = 10k c l = 4pf v out = 1v p-p v out = 100mv p-p v out = 50mv p-p v out = 10mv p-p v out = 500mv p-p v out = 200mv p-p normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 v + = 2.5v a v = +1 v out = 50mv p-p c l = 4pf 100 1k 10k 100k 1m 10m 100m r l = 1k r l = 100 r l = 4.99k r l = 499 normalized gain (db) frequency (hz) -4 -2 0 2 4 6 8 10 12 14 1k 10k 100k 1m 10m v s = 2.5v r l = 10k a v = +1 v out = 50mv p-p c l = 474pf c l = 224pf c l = 104pf c l = 26pf c l = 4pf c l = 1004pf normalized gain (db) frequency (hz) 100k 1m 10m 10k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100m c l = 4pf r l = 10k a v = +1 v out = 50mv p-p v s = 2.5v v s = 0.9v v s = 1.25v v s = 1.75v 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m 10m crosstalk (db) frequency (hz) r l -receiver = 10k a v = +1 v source = 1v p-p c l = 4pf r l -driver = inf v s = 2.5v
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 8 of 23 december 8, 2016 figure 14. small signal transient response, v s = 2.5v figure 15. large signal transient response vs r l ,v s = 0.9v, 2.5v figure 16. negative output overload response time, v s = 0.9v, 2.5v figure 17. positive output overload response time, v s = 0.9v, 2.5v figure 18. % overshoot vs load capacitance, v s = 2.5v typical performance curves v s = 2.5v, v cm = 0v, r l = open, unless otherwise specified. (continued) time (ns) small signal (mv) -40 -30 -20 -10 0 10 20 30 0 80 160 240 320 400 480 560 640 720 800 r l = 10k a v = +1 c l = 15pf v out = 50mv p-p v s = 2.5v -3 -2 -1 0 1 2 3 012345678910 time (s) large signal (v) r l = 10k a v = +1 c l = 15pf v out = rail v s = 0.9v v s = 2.5v time (ms) input (v) output (v) -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0 input r l = inf a v =10 c l = 15pf r f = 9.09k, r g = 1k output at v s = 0.9v output at v s = 2.5v -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 time (ms) input (v) -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 output (v) input r l = inf a v = 10 c l = 15pf r f = 9.09k, r g = 1k output at v s = 0.9v output at v s = 2.5v 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1k 10k capacitance (pf) overshoot (%) o v e r s h o o t + v s = 2.5v r l = 10k a v = 1 v out = 50mv p-p o v e r s h o o t -
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 9 of 23 december 8, 2016 applications information functional description the isl28114, isl28214 and isl28414 are single, dual, and quad, cmos rail-to-rail input, output (rrio) micropower operational amplifiers. they are de signed to operate from single supply (1.8v to 5.5v) or dual supply (0.9v to 2.75v). the parts have an input common-mode range that extends 100mv above and below the power supply voltage rails. the output stage can swing to within 15mv of the supply rails with a 10k load. input esd diode protection all input terminals have internal esd protection diodes to both positive and negative supply rail s, limiting the input voltage to within one diode beyond the suppl y rails. for applications where the input differential voltage is expected to exceed 0.5v, an external series resistor must be used to ensure the input currents never exceed 20ma (see figure 19 ). output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl28114, isl28214, and isl28414 are immune to output phase reversal, even when the input voltage is 1v beyond the supplies. unused channels if the application requires le ss than all amplifiers on one channel, the user must configure the unused channel(s) to prevent oscillation. the unused channel(s) will oscillate if the input and output pins are floating. this will result in higher than expected supply currents and po ssible noise injection into the channel being used. the proper way to prevent this oscillation is to short the output to the inverting input and ground the positive input (as shown in figure 20 ). power dissipation it is possible to exceed the +125c maximum junction temperatures under certain load, power supply conditions, and ambient temperature conditions. it is therefore important to calculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package types need to be modified to remain in the safe operating area. these parameters are related using equation 1 : where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2 : where: ?t max = maximum ambient temperature ? ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent suppl y current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance isl28114, isl28214, and isl28414 spice model figure 21 on page 11 shows the spice model schematic and figure 22 on page 12 shows the net list for the spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. ac parameters incorporated into the model are: 1/f and flatband noise, slew rate, cmrr, gain, and phase. the dc parameters ar e ios, total supply current, and output voltage swing. the model us es typical parameters given in the ?electrical specifications? table beginning on page 4 . the avol is adjusted for 90db with th e dominate pole at 125hz. the cmrr is set 72db, f = 80khz. the input stage models the actual device to present an accurate ac representation. the model is configured for ambient temperature of +25c. figures 23 through 30 show the characteriza tion vs simulation results for the noise voltage, closed loop gain vs frequency, large signal 5v step response , and cmrr and open-loop gain phase. figure 19. input esd diode current limiting - + r in - r l v in - v+ v- r in + r f r g figure 20. preventing oscillations in unused channels - + t jmax t max ? ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ? - v outmax ? v outmax r l ------------------------ ? + ? = (eq. 2)
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 10 of 23 december 8, 2016 license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable license to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including, but not limited to , any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and th e macro-model without prior notice.
fn6800 rev 10.00 page 11 of 23 december 8, 2016 isl28114, isl28214, isl28414 . in- in+ common mode gain stage with zero correction current sources output stage pole stage input stage 1st gain stage mid supply ref v voltage noise stage 2nd gain stage 28 7 20 13 2 vin+ 22 22 vin- 11 6 21 21 17 26 vmid v- 5 18 v-- v+ 3 vout 27 en vc 8 v++ 23 29 15 14 14 14 14 4 12 10 19 9 16 vg vcm 24 25 0 0 0 0 v1 1e-6 v1 1e-6 ra1 1 ra1 1 + - g8 gain = 6.283e-4 + - g8 gain = r6 10 r6 10 m15 nchannelmosfet m15 nchannelmosfet v8 .08 v8 .08 r10 1e9 r10 1e9 + - g2a gain = + - g2a gain = 351 r2 4.0004 r2 r14 636.6588k r14 636.6588k dy d12 dy d12 + - g5 gain = 2.5118e-08 + - g5 gain = 2.5118e-08 + - g4 gain = 24.89e-3 + - g4 gain = 24.89e-3 cin1 1.26e-12 cin1 1.26e-12 c5 10e-12 c5 10e-12 cin2 1.26e-12 cin2 1.26e-12 dx d1 dx d1 m17 pmosisil m17 pmosisil c4 10e-12 c4 10e-12 dx d3 dx d3 dy d11 dy d11 r20 50 r20 50 v7 .08 v7 .08 - + + - e2 gain = 1 - + + - e2 gain = 1 dx d10 dx d10 + - g9 gain = 0.02 + - g9 gain = 0.02 r17 1591.596 r17 i1 5e-3 i1 5e-3 + - g6 gain = 2.5118e-08 + - g6 gain = 2.5118e-08 cindif 1.02e-12 cindif 1.02e-12 r7 4 r7 r5 10 r5 10 v4 .61 v4 .61 + - g11 gain = 0.02 + - g11 gain = 0.02 - + + - e3 gain = 1 - + + - e3 gain = 1 r12 1 r12 1 dx d2 dx d2 r15 10e3 r15 10e3 r13 636.6588k r13 636.6588k dx d4 dx d4 r21 30 r21 30 v2 1e-6 v2 1e-6 v9 0.425 v9 0.425 l2 15.9159e-3 l2 15.9159e-3 r9 100 r9 100 ra2 1 ra2 1 v3 .61 v3 .61 dx d7 dx d7 dx d9 dx d9 + - g2 gain = 334.753e-3 + - g2 gain = 334.753e-3 r25 10 r25 10 r23 5e11 r23 5e11 r11 1 r11 1 m16 pmosisil m16 pmosisil - + + - en gain = 1 - + + - en gain = 1 + - g3 gain = 24.89e-3 + - g3 gain = 24.89e-3 + - g12 gain = 0.02 + - g12 gain = 0.02 ios1 25e-12 ios1 25e-12 m14 nchannelmosfet m14 nchannelmosfet r8 4 r8 r16 10e3 r16 10e3 + - g10 gain = 0.02 + - g10 gain = 0.02 + - g7 gain = 6.283e-4 + - g7 gain = dx d6 dx d6 r19 50 r19 50 l1 15.9159e-3 l1 15.9159e-3 dx d5 dx d5 - + + - e4 - + + - e4 dx d8 dx d8 - + + - eos gain = 1e-3 - + + - eos gain = r22 5e11 r22 5e11 isy 300e-6 isy 300e-6 r1 4.0004 r1 + - g1 gain = 334.753e-3 + - g1 gain = 334.753e-3 i2 5e-3 i2 5e-3 r18 1591.596 r18 + - g1a gain = 351 + - g1a gain = v6 .604 v6 .604 r24 10 r24 10 v5 .604 v5 .604 c2 2e-9 c2 2e-9 c3 2e-9 c3 2e-9 dn d13 dn d13 figure 21. spice schematic
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 12 of 23 december 8, 2016 figure 22. spice net list *isl28114 macromodel - covers following *products *isl28114 *isl28214 *isl28414 ** *revision history: *revision c, lafontaine october 20th 2011 *model for noise to match measured part, * quiescent supply currents, *cmrr 72db *fcm=100khz, avol 90db f=125hz, sr = *2.5v/us, gbwp 5mhz, 2nd pole 10mhz output voltage clamp and short ckt current *limit. ** *copyright 2011 by intersil corporation *refer to data sheet "license *statement" use of this model indicates *your acceptance with the terms and *provisions in the license statement. * *intended use: *this pspice macromodel is intended to give *typical dc and ac performance *characteristics under a wide range of *external circuit configurations using *compatible simulation platforms - such as *isim pe. * *device performance features supported by *this model: *typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *open and closed loop i/o impedances *open loop gain and phase *closed loop bandwidth and frequency *response *loading effects on closed loop frequency *response *input noise terms including 1/f effects *slew rate *input and output headroom limits to i/o *voltage swing *supply current at nominal specified supply *voltages ** *device performance features not *supported by this model *harmonic distortion effects *disable operation (if any) *thermal effects and/or over temperature *parameter variation *limited performance variation vs. supply *voltage is modeled *part to part performance variation due to *normal process parameter spread *any performance difference arising from *different packaging * source * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28114 vin+ vin- v+ v- vout * source isl28114_ds rev2 * *voltage noise e_en vin+ en 28 0 1 d_d13 29 28 dn v_v9 29 0 0.425 r_r21 28 0 30 * *input stage m_m14 3 1 5 5 nchannelmosfet m_m15 4 vin- 6 6 nchannelmosfet m_m16 11 vin- 9 9 pmosisil m_m17 12 1 10 10 pmosisil i_i1 7 v-- dc 5e-3 i_i2 v++ 8 dc 5e-3 i_ios vin- 1 dc 25e-12 g_g1a v++ 14 4 3 351 g_g2a v-- 14 11 12 351 v_v1 v++ 2 1e-6 v_v2 13 v-- 1e-6 r_r1 3 2 4.0004 r_r2 4 2 4.0004 r_r3 5 7 10 r_r4 7 6 10 r_r5 9 8 10 r_r6 8 10 10 r_r7 13 11 4 r_r8 13 12 4 r_ra1 14 v++ 1 r_ra2 v-- 14 1 c_cindif vin- en 1.02e-12 c_cin1 v-- en 1.26e-12 c_cin2 v-- vin- 1.26e-12 * *1st gain stage g_g1 v++ 16 15 vmid 334.753e-3 g_g2 v-- 16 15 vmid 334.753e-3 v_v3 17 16 .61 v_v4 16 18 .61 d_d1 15 vmid dx d_d2 vmid 15 dx d_d3 17 v++ dx d_d4 v-- 18 dx r_r9 15 14 100 r_r10 15 vmid 1e9 r_r11 16 v++ 1 r_r12 v-- 16 1 * *2nd gain stage g_g3 v++ vg 16 vmid 24.893e-3 g_g4 v-- vg 16 vmid 24.893e-3 v_v5 19 vg .604 v_v6 vg 20 .604 d_d5 19 v++ dx d_d6 v-- 20 dx r_r13 vg v++ 636.658e3 r_r14 v-- vg 636.658e3 c_c2 vg v++ 2e-09 c_c3 v-- vg 2e-09 * *mid supply ref e_e4 vmid v-- v++ v-- 0.5 e_e2 v++ 0 v+ 0 1 e_e3 v-- 0 v- 0 1 i_isy v+ v- dc 300e-6 * *common mode gain stage with zero g_g5 v++ vc vcm vmid 2.5118e-8 g_g6 v-- vc vcm vmid 2.5118e-8 e_eos 1 en vc vmid 1e-3 r_r15 vc 21 10e3 r_r16 22 vc 10e3 r_r22 en vcm 5e11 r_r23 vcm vin- 5e11 l_l1 21 v++ 15.9159e-3 l_l2 22 v-- 15.9159e-3 * *pole stage g_g7 v++ 23 vg vmid 6.283e-4 g_g8 v-- 23 vg vmid 6.283e-4 r_r17 23 v++ 1591.596 r_r18 v-- 23 1591.596 c_c4 23 v++ 10e-12 c_c5 v-- 23 10e-12 * *output stage with correction current sources g_g9 26 v-- vout 23 0.02 g_g10 27 v-- 23 vout 0.02 g_g11 vout v++ v++ 23 0.02 g_g12 v-- vout 23 v-- 0.02 v_v7 24 vout .08 v_v8 vout 25 .08 d_d7 23 24 dx d_d8 25 23 dx d_d9 v++ 26 dx d_d10 v++ 27 dx d_d11 v-- 26 dy d_d12 v-- 27 dy r_r19 vout v++ 50 r_r20 v-- vout 50 .model pmosisil pmos (kp=16e-3 vto=-0.6) .model nchannelmosfet nmos (kp=3e-3 vto=0.6) .model dn d(kf =6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28114
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 13 of 23 december 8, 2016 characterization vs simulation results figure 23. characterized input noise voltage figure 24. simulated input noise voltage figure 25. characterized clos ed-loop gain vs frequency figure 26. simulated closed -loop gain vs frequency figure 27. characterized large signal transient response vs r l , v s = 0.9v, 2.5v figure 28. simulated large sign al transient response vs r l , v s = 0.9v, 2.5v frequency (hz) 10 100 1000 input noise voltage (nv/ ? hz) 1 10 100 1k 10k 100k 10,000 v + = 2.5v a v = 1 frequency (hz) 10 100 1000 input noise voltage (nv/ ? hz) 1 10 100 1k 10k 100k 10,000 v + = 2.5v a v = 1 frequency (hz) gain (db) 100k 1m 10m 10 10k 1k 100 70 -10 0 10 20 30 40 50 60 100m v + = 2.5v v out = 50mv p-p c l = 4pf r l = 10k a v = 1 a v = 100 a v = 1000 r g = 100, r f = 100k r g = 10k, r f = 100k r g = 1k, r f = 100k a v = 10 r g = open, r f = 0 (a) ac sims.dat (active) frequency (hz) 10 100 1k 10k 100k 1.0m 10m 100m 0 20 40 60 -10 70 a v = 100 a v = 1000 r g = 100, r f = 100k r g = 10k, r f = 100k a v = 10 r g = 1k, r f = 100k r g = 100k, r f = 100k gain (db) -3 -2 -1 0 1 2 3 012345678910 time (s) r l = 10k a v = +1 c l = 15pf v out = rail v s = 0.9v v s = 2.5v large signal (v) (a) ac sims.dat (active) time (s) 5 10 15 20 25 30 -3 -2 -1 -0 1 2 3 0 r l = 10k a v = +10 c l = 15pf v out = rail v s = 2.5v v out v in large signal (v) v(vin+)/vout)
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 14 of 23 december 8, 2016 figure 29. simulated (design) open-loop gain, phase vs frequency figure 30. simulated (spice) open-loop gain, phase vs frequency figure 31. simulated (design) cmrr figure 32. simulated (spice) cmrr characterization vs simulation results (continued) -80 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open-loop gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 phase () r l = 100k simulation c l = 10pf phase gain v + = 0.9v (a) ac2.dat (active) frequency (hz) 0.01 0.1 1.0 10 100 1.0k 10k 100k 1m 10m 100m 0 40 80 120 160 200 gain r l = 10k model vos set to zero c l = 10pf for this test phase open-loop gain (db)/phase () 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db) simulation (a) ac sims.dat (active) 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db)
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 15 of 23 december 8, 2016 revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change december 8, 2016 fn6800.10 updated related literature section. updated third applications bullet. updated ordering information table on page 2. june 11, 2015 fn6800.9 electrical spec table, page 5 - input no ise voltage density (en) adde d a spec at 10khz (typical spec). october 26, 2012 fn6800.8 added sot23-8 package on page 1 to description and features. ordering information on page 2 - added isl28214fhz parts and note 5 reference. added lead finish note to ordering information for 8 ld sot-23 parts. thermal information on page 4 - added 8 ld sot-23 package with tja and tjc added p8.064 pod on page 23. april 13, 2012 fn6800.7 changed the low supply current in ?features? and description on page 1 from 360a to 390a. removed isl28114fev1z-t7 coming soon parts from ?ordering information? on page 2. removed applicable pinout from page 3. on page 4, changed min/max limits for ?v os ? at 25c from -5/5mv to -4/4mv. on page 4, changed min/max limits for ?v os ? at -40c to 125c from -6/6mv to -5/5mv. on page 4, changed ?tcv os ? typ from 2v/c to 5v/c. on page 4, changed max limit for ?i s ? max at 25c from 360a to 390a. on page 4, changed max limit for ?i s ? max at -40c to 125c from 400a to 475a. revised figure 8 on page 7. revised figure 11 on page 7. revised figure 18 on page 8. january 3, 2012 fn6800.6 revised ?spice schemati c? on page 11 and ?spice net list? on page 12. may 18, 2011 fn6800.5 - on page 3, pin descriptions: circuit 3 diagram, removed anti-parallel diodes from the in+ to in- terminals. - on page 4, absolute maximum ratings: changed differential input voltage from "0.5v" to "v- - 0.5v to v+ + 0.5v" - on page 4, updated cmrr and psrr parameters in electrical specifications table with test condition specifying -40c to 125c typical parameter. - on page 5, updated note 8, referenced in min and max column headings of electrical specifications table, from "parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested." to new standard "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." - on page 9, under ?input esd diode protectio n,? removed ?they also contain back to-back diodes across the input terminals.? removed ?although the amplifier is fully protected, high input slew rates that exceed the amplifier slew rate (2.5v/s) may cause output distortion.? - on page 9, figure 19: updated circuit schematic by removing back-to-back input protection diodes. - on page 11 replaced spice schematic (figure 21) - on page 12 replaced spice netlist (figure 22) - on page 13 replaced figure 24 - on page 14 replaced figure 32
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 16 of 23 december 8, 2016 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related docume ntation, and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . september 23, 2010 fn6800.4 added new sc70 pinout package extension as follows: added to related literature on page 1 ?see an1547 for ?isl28414tssopeval1z evaluation board user?s guide?. added to ordering informatio n isl28114fev1z-t7 and isl28114fev1z-t7a and evaluation boards. added to pin configurations new pinout for isl28114fev1z. added in pin descriptions isl28114fev1z sc70 pin description column. changed note 7 on page page 4 from ?for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside.? to ?for ? jc , the ?case temp? location is taken at the package top center.? added ?related literature? on page 1. changed package outline drawing from mdp0038 to p5.064a on page 2 and page 18. mdp0038 package contained 2 packages for both the 5 and 6 ld sot-23. mdp0038 was obsoleted and the packages were separated and made into 2 separate package outline drawings; p5.064a and p6.064a. changes to the 5 ld sot-23 were to move dimensions from table onto drawing, add land pattern and add jedec reference number. added note 5 to ?ordering information? on page 2. december 16, 2009 fn6800.3 removed ?coming soon? from msop package options in the ?ordering information? on page 2. updated the theta ja for the msop package option from 170c/w to 180c/w on page 4. november 17, 2009 fn6800.2 removed ?coming soon? from sc70 and sot-23 package options in the ?ordering information? on page 2. november 12, 2009 fn6800.1 changed theta ja to 250 from 300. a dded license statement (page 10) and reference in spice model (page 12). october 23, 2009 fn6800.0 initial release revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. (continued) date revision change
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 17 of 23 december 8, 2016 small outline transistor plastic packages (sc70-5) d e 1 e e1 c l c c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 4 5 123 view c view c l r1 r 4x ? 1 4x ? 1 gauge plane l1 seating ? l2 c plane c base metal with c1 b1 plating b 0.4mm 0.75mm 0.65mm 2.1mm typical recommended land pattern p5.049 5 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.031 0.043 0.80 1.10 - a1 0.000 0.004 0.00 0.10 - a2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 d 0.073 0.085 1.85 2.15 3 e 0.071 0.094 1.80 2.40 - e1 0.045 0.053 1.15 1.35 3 e 0.0256 ref 0.65 ref - e1 0.0512 ref 1.30 ref - l 0.010 0.018 0.26 0.46 4 l1 0.017 ref. 0.420 ref. - l2 0.006 bsc 0.15 bsc ? 0 o 8 o 0 o 8 o - n5 55 r 0.004 - 0.10 - r1 0.004 0.010 0.15 0.25 rev. 3 7/07 notes: 1. dimensioning and tolerances per asme y14.5m-1994. 2. package conforms to eiaj sc70 and jedec mo-203aa. 3. dimensions d and e1 are exclusive of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. n is the number of terminal positions. 6. these dimensions apply to the flat section of the lead betwee n 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: milli meter. converted inch dimen- sions are for reference only. for the most recent package outline drawing, see p5.049 .
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 18 of 23 december 8, 2016 package outline drawing p5.064a 5 lead small outline tran sistor plastic package rev 0, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs . this dimension is measured at datum h. package conforms to jedec mo-178aa. foot length is measured at r eference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 1.60 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.20 see detail x 1.45 max (0.60) 0-3 c b a d 3 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 5 2 4 5 5 end view plane for the most recent package outline drawing, see p5.064a .
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 19 of 23 december 8, 2016 package outline drawing m8.118a 8 lead mini small outline plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions d and e1 are measured at datum plane h. this replaces existing drawing # mdp0043 msop 8l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to jedec mo-187-aa 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view side view 2 included. included. gauge plane 33 0.25 c a b b 0.10 c 0.08 c a b a 0.25 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 4.40 3.00 5.80 0.65 3.00.1 4.90.15 1.40 0.40 0.65 bsc pin# 1 id detail "x" 0.33 +0.07/ -0.08 0.10 0.05 3.00.1 1 2 8 0.860.09 seating plane and amse y14.5m-1994. for the most recent package outline drawing, see m8.118a .
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 20 of 23 december 8, 2016 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise s pecified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side . dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view a typical recomme nded land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view b for the most recent package outline drawing, see m8.15e .
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 21 of 23 december 8, 2016 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail x c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150) so16 (0.300) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ? 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ? 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ? 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ? 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ? 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ? 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ? 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ? 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions o f 0.006 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions d and e1 are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994 for the most recent package outline drawing, see mdp0027 .
isl28114, isl28214, isl28414 fn6800 rev 10.00 page 22 of 23 december 8, 2016 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail x end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension e1 does not include interlead flash or protrusion s. interlead flash and protrusions shall not exceed 0.25mm per side. 3. dimensions d and e1 are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994. for the most recent package outline drawing, see mdp0044 .
fn6800 rev 10.00 page 23 of 23 december 8, 2016 isl28114, isl28214, isl28414 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline transistor plastic packages (sot23-8) d e 1 e c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 1234 5 6 87 e1 c l c view c view c l r1 r 4x ? 1 4x ? 1 gauge plane l1 seating ? l2 c plane c base metal with c1 b1 plating b p8.064 8 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.036 0.057 0.90 1.45 - a1 0.000 0.0059 0.00 0.15 - a2 0.036 0.051 0.90 1.30 - b 0.009 0.015 0.22 0.38 - b1 0.009 0.013 0.22 0.33 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 d 0.111 0.118 2.80 3.00 3 e 0.103 0.118 2.60 3.00 - e1 0.060 0.067 1.50 1.70 3 e 0.0256 ref 0.65 ref - e1 0.0768 ref 1.95 ref - l 0.014 0.022 0.35 0.55 4 l1 0.024 ref. 0.60 ref. l2 0.010 ref. 0.25 ref. n8 85 r 0.004 - 0.10 - r1 0.004 0.010 0.10 0.25 ? 0 o 8 o 0 o 8 o - rev. 2 9/03 notes: 1. dimensioning and tolerance per asme y14.5m-1994. 2. package conforms to eiaj sc-74 and jedec mo178ba. 3. dimensions d and e1 are exclusive of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. n is the number of terminal positions. 6. these dimensions apply to the flat section of the lead betwee n 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: milli meter. converted inch dimen- sions are for reference only for the most recent package outline drawing, see p8.064 .

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